Accelerating Two-Dimensional Page Walks for Virtualized Systems

Authors: Ravi Bhargava, Benjamin Serebrin, Francesco Spadini, Srilatha Manne
Venue:    ASPLOS 2008

This paper examines the effects of a virtualization on address translation. It is known that minimizing the number of virtualization exits to the hypervisor is critical for optimal performance. By default, two dimensions of address translation would be needed -- guest VA to guest PA, then guest PA to system PA. By default this is done by a "shadow page table" in software. However, the use of a nested page table enables full translation form guest VA to system PA via hardware. However, added complexity can yield reduced TLB hit rates, which can lead to degradation in performance by up to 70% over native execution.

As such, the authors of this paper introduce Page Walk Cache (PWC), which when used in combination with nested paging, can yield up to a 38% performance improvement (or more referenced outside of the paper).  The authors of this paper perform careful analysis to show exactly what levels of address translation should be cached for maximum effectiveness. They then utilize this information, along with further sensitivity analysis, to design a their PWC and Nested TLB MMU. Further analysis also shows that use of hugepages can further improve performance.

Note: This paper covers a complex topic, but does a good job at summarizing a large portion of the background. It is highly recommended to reference the original text for a deeper understanding.

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