SHARP Control: Controlled Shared Cache Management in Chip Multiprocessors

Authors: Shekhar Srikantaiah, Mahmut Kandemir, Qian Wang
Venue:    MICRO 2009

This paper presents a new scheme for dynamic cache partition of a shared LLC. SHARP control leverages control their and separates the optimization into two layers: a local, per-core decision and a global, system-wide decision. Formal control theory provides performance guarantees, is resilient to minor inaccuracies, offers quick adaptive response and allows for high-level objects to be easily specified. The authors even provide a sketch of a proof which includes time-varying behavior. Each per-core controller is a reinforced oscillation resistant controller, which dynamically adjusts it's parameters based on the phase-behavior of applications. The global decision in managed in two steps, the PAN controller allocates addition cache ways to prevent under utilization, whereas the SHARP controller makes the decision of where to remove cache ways when the system is over subscribed.

Significant experimentation shows that their model not only is able to boost fair-share speedup, but also prioritize specific applications by a simple weighting function. Overall the most significant improvement seems to come form the choice of using ROR controllers instead of PID controllers. This nets up to 21.9% improvement over Cooperative Partitioning or Utility-based schemes. Despite the seeming complexity of the scheme, an overhead of just 15,000 cycles to update the controller and operate at an interval of 10M cycles.

Misc notes:
Time-varying behavior analysis does include repeating phase behavior but rather just changing behavior that can be adapted to.

High Cache Pressure: apsi, parser, crafty, ammp, perlbmk, mesa
Low Cache Pressure: mcf, gzip, gap, applu, twolf, fma3d

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