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Showing posts with the label machine learning

Post-Silicon CPU Adaptation Made Practical Using Machine Learning

Authors: Stephen J. Tarsa, Gautham Chinya, Hong Wang, et. al. Venue:    ISCA 2019 Preface : Before I begin, I'd like to preface that this is one of my favorite papers of 2019; it is well-written, shows poise in the application of machine learning techniques, and consideration of real-world applicability. I read this paper and produced my own slides for it, which can be found here . Overview: This paper presents an adaptive architecture controlled by a machine learning solution. Adaptive architecture itself is not a novel idea, there have been several works regarding tile-based clock gating, heterogenous core scheduling, pipeline gating, etc. This core chooses a simple adaptive piece of hardware, a binary decision to enable to disable a cluster. In this case, a cluster comprises of instruction cache, a decoder, memory execution unit, register file, ROB, and execution units. The authors hint at this being something like a modern SMT core, which can use all it's resource fo...

PADDLE: Performance Analysis using a Data-Driven Learning Environment

Authors: Jayaraman Thiagarajan, Rushil Anirdh, Bhavya Kaikhura, Nikhil Jain, Tanzima Islam, Abhinav Bhatele, Jae-Seung Yeom, Todd Gamblin Venue: I EEE International Parallel and Distributed Processing Symposium (IPDPS) In the scope of HPC, machine learning is gaining increased traction to add in performance analysis and tuning. However, this approach includes a pipeline of data collection, data pre-processing, various machine learning algorithm testing, tuning, and then finally trying to understand the model. The paper states that while this process is repetitive, rarely can insights be reused from one domain to another. To address this void, the propose PADDLE. PADDLE has three key steps: deep feature extraction, model design, and visualization. The first step allows users to throw extensive amounts of data at the problem, and an automated solutions determines the key inputs, mapping them to a new feature space. The next step in paddle automatically tests a number of machine lea...