Karl Taht's Research Paper Blog

Authors: Ravi Bhargava, Benjamin Serebrin, Francesco Spadini, Srilatha Manne Venue:    ASPLOS 2008 This paper examines the effects of a virtualization on address translation. It is known that minimizing the number of virtualization exits to the hypervisor is critical for optimal performance. By default, two dimensions of address translation would be needed -- guest VA to guest PA, then guest PA to system PA. By default this is done by a "shadow page table" in software. However, the use of a nested page table enables full translation form guest VA to system PA via hardware. However, added complexity can yield reduced TLB hit rates, which can lead to degradation in performance by up to 70% over native execution. As such, the authors of this paper introduce  Page Walk Cache  (PWC), which when used in combination with nested paging, can yield up to a 38% performance improvement (or more referenced outside of the paper).  The authors of this paper perform carefu...

Authors: Luiz Barroso, Mike Marty, David Patterson, and Parthasarathy Ranganathan Venue:    CACM (Magazine) This work shows that while architects have tackled problems and the nanosecond scale, and software has optimized for the millisecond scale, there exists a significant void in microsecond operation optimization. The result is that many operations which take in the order of a few microseconds degenerate into millisecond operations, or at least, reduce efficiency by up to or more than an order of magnitude in many cases. One such example is an RDMA, which by itself is only a ~2us operation. However, after dispatching, kernel-scheduling, interrupt-based notifications, and a TCP/IP stack, the transportation blows up to ~75us. The authors imply that this area is prime for research to optimize warehouse-scale computing. Such areas include reduced lock contention, lower-overhead interrupt handling, improved scheduling, and hardware-offloading in the mi...