Karl Taht's Research Paper Blog

Authors: Archana Ganapathi, Kaushik Datta, Armando Fox, David Patterson Venue: USENIX Hot Topics in Parallelism 2009 This workshop paper examines applying a machine learning technique to auto-tuning HPC stencils. The configuration space consists of 5 independent knobs resulting in a total of ~4 million possible configurations. The work applies KCCA (kernel canonical correlation analysis) which finds correlations between two sets of data, in this case performance measurements and tune settings. KCCA is a specific way to do this that allows for non-linear relationships. Compared to feature extraction techniques, this is a direct way to find correlations rather than just using an intermediate step of feature extraction followed by a method of clustering. The main reason this appears to be only a workshop paper is that only two experiments are performed, both using stencils. The KCCA algorithm is definitely worth a deeper understanding, as the results are promising. Full Text

Authors: Aleksander Maricq, Dmitry Duplyakin, Ivo Jimenez, Carlos Maltzahn, Ryan Stutsman, Robert Ricci Venue: OSDI 2018 This paper performs in-depth statistical analysis to understand the performance variability present in real-systems. The goal is to quantify variability, and understand how to tame it from both a researcher's and cloud provider's perspective. To do so, the authors collect nearly 900,000 data points over the course of 10 months on real systems. A key insight is that the distribution of runs is a non-normal distribution, as such, typical parameterized analysis with closed form solutions should not be applied. In fact, typical analysis using CoV yields significantly different results than those which make no assumptions about the distribution. Thus, the authors make use of non-parameterized techniques to establish confidence intervals and error tolerance. From a researcher's perspective, the authors build a tool which performs such analysis on a given d...

Authors: Jian Lin, Qingda Lu, .. P. Sadayappan et al. Venue:    HPCA 2008 The authors of this paper present an in-depth analysis and optimization of cache partitioning on a real-system. They accomplish this by using OS-page coloring, which induces only ~2% overhead. Since they cite the goal of their study primarily as analysis and potential, they subtract out this overhead. The authors show significant discrepancy compared to previous studies, which they cite as an artifact of simulations which are too small in length, and use too small of datasets. The real system approach allows for much longer runs with larger datasets. Benchmarks are divided into 4 categories: Red : Highly sensitive to cache size (bzip2, mcf, omnetpp, astar, sphinx3, xalanc) Yellow : Moderately sensitive (gcc, leslie3d, soplex, Gems, tonto, lbm, perl, catcus, h264) Green : Marginally sensitive (bwaves, zeus, gromacs, povray, libq, wrf) They create 27 workloads which each comprise of two benchm...

Venue:    MICRO 2016 Authors: Mikhail Kazdagli, Vijay Janapa Reddi, Mohit Tiwari This paper presents an analyze of hardware-based malware detection on a mobile platform, mainly Android. The paper does an exception job at modeling many different malware acts, analyzing not only their behaviors, but validating the attacks are operating correctly. The paper then uses hardware performance counters to detect malware. They note that this malware on mobile devices typically operates in the order of seconds. They create Sherlock, a Hardware Malware Detector (HMD), which samples number of instructions, number of memory loads/stores, immediate and indirect control flow execution counts, and number of mispredicted branches. They sample at a frequency of 1kHz, finding the overhead to be 0.3%. They extract features from each 100ms long time interval using Discrete Wavelet Transform (using the coefficients as a feature vector). They use these feature vectors to construct two models: (a) ...

Authors:   Evelyn Duesterwald, Calin Cascaval, Sandhya Dwarkadas (IBM, Rochester) Venue:      PACT 2003 This paper makes no effort to tune hardware, but shows yet another phase detection and prediction technique. The study is done on real hardware, using IBM Power3 and Power4 architectures. Both of these are extremely outdated, but it makes for an interesting paper nevertheless. They are able to instrument their phase detection techniques on OS interrupts at a granularity of 10ms. At this time, they read various performance counter, analyzing the current hardware state and predicting the future hardware state. It is not entirely clear how they actually determine a phase, but essentially, they are able to accurately predict different performance metrics such as IPC, branch miss-predict rate, and L1 cache miss rate. They support the use of table-based predictor. They also show that most statistics are extremely correlated, so a predictor for one metric can li...