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Showing posts with the label performance modeling

Understanding and Auto-Adjusting Performance-Sensitive Configurations

Authors: Shu Wang, Chi Li, Henry Hoffman, Shan Lu, William Sentosa, Achmad Imam Kistijantoro Venue: ASPLOS 2018 This paper presents a control theory approach to solving performance problems in workloads with many configurable parameters. The authors reference database workloads such as Cassandra, HBase, HDFS, and Hadoop MapReduce. The authors employ control theory with two key components outside of traditional control theory: a dynamic pole (error tolerance factor), and a virtual goal. Combined, these two approaches allow SmartConf to meet performance goals and hard constraints better than previous approaches. The authors also go into detail as to how their approach could be integrated into commercial software. See Yukta (ISCA 2018) for a similar-flavor paper which also uses control theory.  The remainder of this post will be subjective. This paper is exceptionally well-written, using many real-world examples to build motivation. Objectively, the paper's novelty is software ...

PADDLE: Performance Analysis using a Data-Driven Learning Environment

Authors: Jayaraman Thiagarajan, Rushil Anirdh, Bhavya Kaikhura, Nikhil Jain, Tanzima Islam, Abhinav Bhatele, Jae-Seung Yeom, Todd Gamblin Venue: I EEE International Parallel and Distributed Processing Symposium (IPDPS) In the scope of HPC, machine learning is gaining increased traction to add in performance analysis and tuning. However, this approach includes a pipeline of data collection, data pre-processing, various machine learning algorithm testing, tuning, and then finally trying to understand the model. The paper states that while this process is repetitive, rarely can insights be reused from one domain to another. To address this void, the propose PADDLE. PADDLE has three key steps: deep feature extraction, model design, and visualization. The first step allows users to throw extensive amounts of data at the problem, and an automated solutions determines the key inputs, mapping them to a new feature space. The next step in paddle automatically tests a number of machine lea...

Predicting inter-thread cache contention on a chip multi-processor architecture

Authors: Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin Venue:    HPCA 2005 The authors present Prob , a model which is able to predict the performance implications of co-locating multiple threads on CMP. The model uses the stack distance profiles / circular sequence profiles as input. Using probability theory, Prob is able to accurately predict the cache miss rates of co-locating programs with an average of ~3.8% accuracy. Moreover, the models accuracy is only significantly off when the performance implications are predicted to be very large, and the real implications are even larger. This is the first work to model the effects of co-locating threads on a CMP, yet is exceedingly accurate. However, the model does not propose a solution to co-locating threads, only a prediction model of the effects. Moreover, the study is done on a two core system -- which was state-of-the-art at time of publication. However, in many-core era the study would be interesting to re-exami...

Modeling Performance Variation Due to Cache Sharing

Authors: Andreas Sandberg, Andreas Sembrant, Erik Hagersten and David Black-Schaffer Venue:    HPCA 2013 The authors of this paper present a modeling framework to predict cache contention when co-locating applications. The model is much lighter weight than previous work, and accurate within 0.41% on average. The authors utilize a three-fold approach: A cache sharing model  - Predicts how much cache is used by an application A cache analysis tool (Cache Pirating)  - Artificially reduces cache size A phase detection framework: (Scarphase)  - Divides applications into phases It should be noted that (1) and (2) can be done directly with what is now Intel RDT, which was not available at the time of publication.     The authors show that co-location of applications exhibits extensive performance variability depending on alignment, particularly when applications exhibit extensive phase behavior. Therefore to predict performance of co-location, a u...